ATmega8(L)
Timer/Counter Interrupt Flag
Register – TIFR
Bit
7
OCF2
R/W
0
6
TOV2
R/W
0
5
ICF1
R/W
0
4
OCF1A
R/W
0
3
OCF1B
R/W
0
2
TOV1
R/W
0
1
–
0
TOV0
R/W
0
TIFR
Read/Write
Initial Value
R/W
0
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt Handling Vector. Alternatively,
TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0
(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the
Timer/Counter0 Overflow interrupt is executed.
71
2486M–AVR–12/03