ATmega8(L)
Figure 32. 16-bit Timer/Counter Block Diagram(1)
Count
TOVn
(Int. Req.)
Clear
Control Logic
Clock Select
Direction
clkTn
Edge
Detector
Tn
TOP
BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
=
= 0
OCFnA
(Int. Req.)
Waveform
Generation
OCnA
=
OCRnA
OCFnB
(Int.Req.)
Fixed
TOP
Values
Waveform
OCnB
=
Generation
OCRnB
( From Analog
Comparator Ouput )
ICFn (Int.Req.)
Edge
Detector
Noise
Canceler
ICRn
ICPn
TCCRnA
TCCRnB
Note:
1. Refer to “Pin Configurations” on page 2, Table 22 on page 56, and Table 28 on page
61 for Timer/Counter1 pin placement and description.
Registers
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture
Register (ICR1) are all 16-bit registers. Special procedures must be followed when
accessing the 16-bit registers. These procedures are described in the section “Access-
ing 16-bit Registers” on page 77. The Timer/Counter Control Registers (TCCR1A/B) are
8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to
Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR).
All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK).
TIFR and TIMSK are not shown in the figure since these registers are shared by other
timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock
source on the T1 pin. The Clock Select logic block controls which clock source and edge
the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is
inactive when no clock source is selected. The output from the clock select logic is
referred to as the timer clock (clk ).
1
T
The double buffered Output Compare Registers (OCR1A/B) are compared with the
Timer/Counter value at all time. The result of the compare can be used by the waveform
generator to generate a PWM or variable frequency output on the Output Compare Pin
(OC1A/B). See “Output Compare Units” on page 83. The Compare Match event will also
75
2486M–AVR–12/03
ATMEL [ ATMEL ]
