ATmega8(L)
Timer/Counter Timing
Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore
shown as a clock enable signal in the following figures. The figures include information
on when Interrupt Flags are set. Figure 28 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value.
Figure 28. Timer/Counter Timing Diagram, No Prescaling
clkI/O
clkTn
(clkI/O/1)
TCNTn
TOVn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
Figure 29 shows the same timing data, but with the prescaler enabled.
Figure 29. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
TOVn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
69
2486M–AVR–12/03
ATMEL [ ATMEL ]
