General Interrupt Flag
Register – GIFR
Bit
7
INTF1
R/W
0
6
INTF0
R/W
0
5
–
4
–
3
–
2
–
1
–
0
–
GIFR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 7 – INTF1: External Interrupt Flag 1
When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one).
If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always
cleared when INT1 is configured as a level interrupt.
• Bit 6 – INTF0: External Interrupt Flag 0
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).
If the I-bit in SREG and the INT0 bit in GICR are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always
cleared when INT0 is configured as a level interrupt.
66
ATmega8(L)
2486M–AVR–12/03
ATMEL [ ATMEL ]
