• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is
written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared
if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow-
ing procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be
written to WDE even though it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the
Watchdog.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
Timeout Periods are shown in Table 17.
Table 17. Watchdog Timer Prescale Select
Number of WDT
Oscillator Cycles
Typical Time-out
at VCC = 3.0V
Typical Time-out
at VCC = 5.0V
WDP2
WDP1
WDP0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16K (16,384)
32K (32,768)
17.1 ms
34.3 ms
68.5 ms
0.14 s
0.27 s
0.55 s
1.1 s
16.3 ms
32.5 ms
65 ms
0.13 s
0.26 s
0.52 s
1.0 s
64K (65,536)
128K (131,072)
256K (262,144)
512K (524,288)
1,024K (1,048,576)
2,048K (2,097,152)
2.2 s
2.1 s
The following code example shows one assembly and one C function for turning off the
WDT. The example assumes that interrupts are controlled (for example, by disabling
interrupts globally) so that no interrupts will occur during execution of these functions.
42
ATmega8(L)
2486M–AVR–12/03
ATMEL [ ATMEL ]
