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ATMEGA8-16AI 参数 Datasheet PDF下载

ATMEGA8-16AI图片预览
型号: ATMEGA8-16AI
PDF下载: 下载PDF文件 查看货源
内容描述: 位的AVR微控制器8K字节在 - 系统内可编程Flash [-bit AVR Microcontroller with 8K Bytes In- System Programmable Flash]
分类和应用: 微控制器
文件页数/大小: 303 页 / 5122 K
品牌: ATMEL [ ATMEL ]
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ATmega8(L)  
Receive Compete Flag and  
Interrupt  
The USART Receiver has one flag that indicates the Receiver state.  
The Receive Complete (RXC) Flag indicates if there are unread data present in the  
receive buffer. This flag is one when unread data exist in the receive buffer, and zero  
when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver  
is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit  
will become zero.  
When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART  
Receive Complete Interrupt will be executed as long as the RXC Flag is set (provided  
that global interrupts are enabled). When interrupt-driven data reception is used, the  
receive complete routine must read the received data from UDR in order to clear the  
RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates.  
Receiver Error Flags  
The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and  
Parity Error (PE). All can be accessed by reading UCSRA. Common for the error flags is  
that they are located in the receive buffer together with the frame for which they indicate  
the error status. Due to the buffering of the error flags, the UCSRA must be read before  
the receive buffer (UDR), since reading the UDR I/O location changes the buffer read  
location. Another equality for the error flags is that they can not be altered by software  
doing a write to the flag location. However, all flags must be set to zero when the  
UCSRA is written for upward compatibility of future USART implementations. None of  
the error flags can generate interrupts.  
The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable  
frame stored in the receive buffer. The FE Flag is zero when the stop bit was correctly  
read (as one), and the FE Flag will be one when the stop bit was incorrect (zero). This  
flag can be used for detecting out-of-sync conditions, detecting break conditions and  
protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRC  
since the Receiver ignores all, except for the first, stop bits. For compatibility with future  
devices, always set this bit to zero when writing to UCSRA.  
The Data OverRun (DOR) Flag indicates data loss due to a Receiver buffer full condi-  
tion. A Data OverRun occurs when the receive buffer is full (two characters), it is a new  
character waiting in the Receive Shift Register, and a new start bit is detected. If the  
DOR Flag is set there was one or more serial frame lost between the frame last read  
from UDR, and the next frame read from UDR. For compatibility with future devices,  
always write this bit to zero when writing to UCSRA. The DOR Flag is cleared when the  
frame received was successfully moved from the Shift Register to the receive buffer.  
The Parity Error (PE) Flag indicates that the next frame in the receive buffer had a parity  
error when received. If parity check is not enabled the PE bit will always be read zero.  
For compatibility with future devices, always set this bit to zero when writing to UCSRA.  
For more details see “Parity Bit Calculation” on page 135 and “Parity Checker” on page  
144.  
143  
2486M–AVR–12/03  
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