ATmega8(L)
5. This requirement applies to all ATmega8 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial
Bus need only obey the general fSCL requirement
6. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than
6MHz for the low time requirement to be strictly met at fSCL = 100kHz
7. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement
will not be strictly met for fSCL > 308kHz when fCK = 8MHz. Still, ATmega8 devices connected to the bus may communicate at
full speed (400kHz) with other ATmega8 devices, as well as any other device with a proper tLOW acceptance margin
Figure 115. Two-wire Serial Bus Timing
t
HIGH
t
t
r
of
t
t
LOW
LOW
SCL
SDA
t
t
t
HD;DAT
SU;STA
HD;STA
t
SU;DAT
t
SU;STO
t
BUF
SPI Timing
See Figure 116 on page 240 and Figure 117 on page 240 for details.
Characteristics
Table 102. SPI Timing Parameters
Description
Mode
Min
Typ
Max
See Table 50 on
page 126
1
SCK period
Master
2
3
SCK high/low
Rise/Fall time
Setup
Master
Master
Master
Master
Master
Master
Master
Slave
50ꢀ duty cycle
3.6
10
4
5
Hold
10
6
Out to SCK
SCK to out
SCK to out high
SS low to out
SCK period
SCK high/low(1)
Rise/Fall time
Setup
0.5 • tSCK
10
7
8
10
9
15
ns
10
11
12
13
14
15
16
17
18
Slave
4 • tck
2 • tck
Slave
Slave
1600
Slave
10
10
Hold
Slave
SCK to out
SCK to SS high
SS high to tri-state
SS low to SCK
Slave
15
10
Slave
20
Slave
Salve
2 • tck
Note:
1. In SPI Programming mode the minimum SCK high/low period is:
- 2tCLCL for fCK < 12MHz
- 3tCLCL for fCK > 12MHz
239
2486AA–AVR–02/2013
ATMEL [ ATMEL ]
