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ATMEGA48PA-CCU 参数 Datasheet PDF下载

ATMEGA48PA-CCU图片预览
型号: ATMEGA48PA-CCU
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 20MHz, CMOS, PBGA32, 4 X 4 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, UFBGA-32]
分类和应用: 闪存微控制器
文件页数/大小: 349 页 / 2752 K
品牌: ATMEL [ ATMEL ]
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Toggling the Pin  
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of  
DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.  
Switching Between Input and When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,  
Output  
PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} =  
0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up  
enabled state is fully acceptable, as a high-impedant environment will not notice the dif-  
ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in  
the MCUCR Register can be set to disable all pull-ups in all ports.  
Switching between input with pull-up and output low generates the same problem. The  
user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state  
({DDxn, PORTxn} = 0b11) as an intermediate step.  
Table 31 summarizes the control signals for the pin value.  
Table 31. Port Pin Configurations  
PUD  
DDxn PORTxn (in MCUCR)  
I/O  
Pull-up Comment  
0
0
X
Input  
No  
Tri-state (Hi-Z)  
Pxn will source current if ext. pulled  
low.  
0
0
1
1
1
1
0
1
0
1
Input  
Input  
Yes  
No  
No  
No  
Tri-state (Hi-Z)  
X
X
Output  
Output  
Output Low (Sink)  
Output High (Source)  
Reading the Pin Value  
Independent of the setting of Data Direction bit DDxn, the port pin can be read through  
the PINxn Register bit. As shown in Figure 24, the PINxn Register bit and the preceding  
latch constitute a synchronizer. This is needed to avoid metastability if the physical pin  
changes value near the edge of the internal clock, but it also introduces a delay. Figure  
25 shows a timing diagram of the synchronization when reading an externally applied  
pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min  
respectively.  
Figure 25. Synchronization when Reading an Externally Applied Pin value  
SYSTEM CLK  
XXX  
XXX  
in r17, PINx  
INSTRUCTIONS  
SYNC LATCH  
PINxn  
0x00  
tpd, max  
0xFF  
r17  
tpd, min  
64  
ATmega48/88/168  
2545D–AVR–07/04  
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