Store Program Memory
The Store Program Memory Control and Status Register contains the control bits
Control and Status Register – needed to control the Program memory operations.
SPMCSR
Bit
7
SPMIE
R/W
0
6
5
–
4
RWWSRE
R/W
3
BLBSET
R/W
0
2
PGWRT
R/W
0
1
PGERS
R/W
0
0
SELFPRGEN
RWWSB
SPMCSR
Read/Write
Initial Value
R
0
R
0
R/W
0
0
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the
SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long
as the SELFPRGEN bit in the SPMCSR Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
This bit is for compatibility with devices supporting Read-While-Write. It will always read
as zero in ATmega48.
• Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the ATmega48/88/168 and will always read as zero.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
The functionality of this bit in ATmega48 is a subset of the functionality in
ATmega88/168. If the RWWSRE bit is written while filling the temporary page buffer, the
temporary page buffer will be cleared and the data will be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
The functionality of this bit in ATmega48 is a subset of the functionality in
ATmega88/168. An LPM instruction within three cycles after BLBSET and SELFPRGEN
are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depend-
ing on Z0 in the Z-pointer) into the destination register. See “Reading the Fuse and Lock
Bits from Software” on page 251 for details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction
within four clock cycles executes Page Write, with the data stored in the temporary
buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and
R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no
SPM instruction is executed within four clock cycles. The CPU is halted during the entire
Page Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction
within four clock cycles executes Page Erase. The page address is taken from the high
part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear
upon completion of a Page Erase, or if no SPM instruction is executed within four clock
cycles. The CPU is halted during the entire Page Write operation.
• Bit 0 – SELFPRGEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one
together with either RWWSRE, BLBSET, PGWRT, or PGERS, the following SPM
instruction will have a special meaning, see description above. If only SELFPRGEN is
written, the following SPM instruction will store the value in R1:R0 in the temporary page
buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SELF-
PRGEN bit will auto-clear upon completion of an SPM instruction, or if no SPM
instruction is executed within four clock cycles. During Page Erase and Page Write, the
SELFPRGEN bit remains high until the operation is completed.
250
ATmega48/88/168
2545D–AVR–07/04
ATMEL [ ATMEL ]
