ATmega48/88/168
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the
lower five bits will have no effect.
EEPROM Write Prevents
Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash.
Reading the Fuses and Lock bits from software will also be prevented during the
EEPROM write operation. It is recommended that the user checks the status bit (EEPE)
in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR
Register.
Reading the Fuse and Lock
Bits from Software
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,
load the Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR.
When an LPM instruction is executed within three CPU cycles after the BLBSET and
SELFPRGEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the
destination register. The BLBSET and SELFPRGEN bits will auto-clear upon completion
of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or
no SPM instruction is executed within four CPU cycles. When BLBSET and SELF-
PRGEN are cleared, LPM will work as described in the Instruction set Manual.
Bit
Rd
7
6
5
4
3
2
1
0
–
–
–
–
–
–
LB2
LB1
The algorithm for reading the Fuse Low byte is similar to the one described above for
reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and
set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM instruction is exe-
cuted within three cycles after the BLBSET and SELFPRGEN bits are set in the
SPMCSR, the value of the Fuse Low byte (FLB) will be loaded in the destination register
as shown below.See Table 119 on page 272 for a detailed description and mapping of
the Fuse Low byte.
Bit
Rd
7
6
5
4
3
2
1
0
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When
an LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN
bits are set in the SPMCSR, the value of the Fuse High byte will be loaded in the desti-
nation register as shown below. See Table 118 on page 272 for detailed description and
mapping of the Extended Fuse byte.
Bit
Rd
7
6
5
4
3
2
1
0
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
Similarly, when reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer.
When an LPM instruction is executed within three cycles after the BLBSET and SELF-
PRGEN bits are set in the SPMCSR, the value of the Extended Fuse byte will be loaded
in the destination register as shown below. See Table 119 on page 272 for detailed
description and mapping of the Extended Fuse byte.
Bit
Rd
7
6
5
4
3
2
1
0
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that
are unprogrammed, will be read as one.
Preventing Flash Corruption
During periods of low VCC, the Flash program can be corrupted because the supply volt-
age is too low for the CPU and the Flash to operate properly. These issues are the same
as for board level systems using the Flash, and the same design solutions should be
applied.
251
2545D–AVR–07/04
ATMEL [ ATMEL ]
