ATmega48/88/168
start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trig-
ger event, even if the ADC Interrupt Flag is set.
Table 102. ADC Auto Trigger Source Selections
ADTS2
ADTS1
ADTS0
Trigger Source
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter0 Compare Match A
Timer/Counter0 Overflow
Timer/Counter1 Compare Match B
Timer/Counter1 Overflow
Timer/Counter1 Capture Event
Digital Input Disable Register
0 – DIDR0
Bit
7
–
6
–
5
ADC5D
R/W
0
4
ADC4D
R/W
0
3
ADC3D
R/W
0
2
ADC2D
R/W
0
1
ADC1D
R/W
0
0
ADC0D
R/W
0
DIDR0
Read/Write
Initial Value
R
0
R
0
• Bits 7:6 – Res: Reserved Bits
These bits are reserved for future use. To ensure compatibility with future devices, these
bits must be written to zero when DIDR0 is written.
• Bit 5..0 – ADC5D..ADC0D: ADC5..0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is
disabled. The corresponding PIN Register bit will always read as zero when this bit is
set. When an analog signal is applied to the ADC5..0 pin and the digital input from this
pin is not needed, this bit should be written logic one to reduce power consumption in
the digital input buffer.
Note that ADC pins ADC7 and ADC6 do not have digital input buffers, and therefore do
not require Digital Input Disable bits.
245
2545D–AVR–07/04
ATMEL [ ATMEL ]
