Table 99. Voltage Reference Selections for ADC
REFS1
REFS0 Voltage Reference Selection
0
0
1
1
0
1
0
1
AREF, Internal Vref turned off
AVCC with external capacitor at AREF pin
Reserved
Internal 1.1V Voltage Reference with external capacitor at AREF pin
•
Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data
Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right
adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately,
regardless of any ongoing conversions. For a complete description of this bit, see “The
ADC Data Register – ADCL and ADCH” on page 244.
• Bit 4 – Res: Reserved Bit
This bit is an unused bit in the ATmega48/88/168, and will always read as zero.
• Bits 3:0 – MUX3:0: Analog Channel Selection Bits
The value of these bits selects which analog inputs are connected to the ADC. See
Table 100 for details. If these bits are changed during a conversion, the change will not
go in effect until this conversion is complete (ADIF in ADCSRA is set).
Table 100. Input Channel Selections
MUX3..0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Single Ended Input
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
1.1V (VBG
)
0V (GND)
ADC Control and Status
Register A – ADCSRA
Bit
7
6
5
4
3
2
1
0
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
ADCSRA
242
ATmega48/88/168
2545D–AVR–07/04
ATMEL [ ATMEL ]
