Figure 90. Formats and States in the Master Transmitter Mode
MT
Successfull
S
SLA
W
A
DATA
A
P
transmission
to a slave
receiver
$08
$18
$28
Next transfer
started with a
repeated start
condition
RS
SLA
W
R
$10
Not acknowledge
received after the
slave address
A
P
$20
MR
Not acknowledge
received after a data
byte
A
P
$30
Arbitration lost in slave
address or data byte
Other master
continues
Other master
continues
A or A
A or A
$38
A
$38
Arbitration lost and
addressed as slave
Other master
continues
To corresponding
states in slave mode
$68 $78 $B0
Any number of data bytes
and their associated acknowledge bits
From master to slave
From slave to master
DATA
A
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
n
216
ATmega48/88/168
2545D–AVR–07/04
ATMEL [ ATMEL ]
