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ATMEGA48PA-CCU 参数 Datasheet PDF下载

ATMEGA48PA-CCU图片预览
型号: ATMEGA48PA-CCU
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 20MHz, CMOS, PBGA32, 4 X 4 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, UFBGA-32]
分类和应用: 闪存微控制器
文件页数/大小: 349 页 / 2752 K
品牌: ATMEL [ ATMEL ]
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Figure 89. Data Transfer in Master Transmitter Mode  
VCC  
Device 1  
MASTER  
TRANSMITTER  
Device 2  
SLAVE  
RECEIVER  
Device 3  
Device n  
R1  
R2  
........  
SDA  
SCL  
A START condition is sent by writing the following value to TWCR:  
TWCR  
TWINT  
TWEA  
TWSTA  
TWSTO  
TWWC  
TWEN  
TWIE  
value  
1
X
1
0
X
1
0
X
TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one  
to transmit a START condition and TWINT must be written to one to clear the TWINT  
Flag. The TWI will then test the 2-wire Serial Bus and generate a START condition as  
soon as the bus becomes free. After a START condition has been transmitted, the  
TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see Table  
91). In order to enter MT mode, SLA+W must be transmitted. This is done by writing  
SLA+W to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to  
continue the transfer. This is accomplished by writing the following value to TWCR:  
TWCR  
TWINT  
TWEA  
TWSTA  
TWSTO  
TWWC  
TWEN  
TWIE  
value  
1
X
0
0
X
1
0
X
When SLA+W have been transmitted and an acknowledgement bit has been received,  
TWINT is set again and a number of status codes in TWSR are possible. Possible sta-  
tus codes in Master mode are 0x18, 0x20, or 0x38. The appropriate action to be taken  
for each of these status codes is detailed in Table 91.  
When SLA+W has been successfully transmitted, a data packet should be transmitted.  
This is done by writing the data byte to TWDR. TWDR must only be written when  
TWINT is high. If not, the access will be discarded, and the Write Collision bit (TWWC)  
will be set in the TWCR Register. After updating TWDR, the TWINT bit should be  
cleared (by writing it to one) to continue the transfer. This is accomplished by writing the  
following value to TWCR:  
TWCR  
TWINT  
TWEA  
TWSTA  
TWSTO  
TWWC  
TWEN  
TWIE  
value  
1
X
0
0
X
1
0
X
This scheme is repeated until the last byte has been sent and the transfer is ended by  
generating a STOP condition or a repeated START condition. A STOP condition is gen-  
erated by writing the following value to TWCR:  
TWCR  
TWINT  
TWEA  
TWSTA  
TWSTO  
TWWC  
TWEN  
TWIE  
value  
1
X
0
1
X
1
0
X
A REPEATED START condition is generated by writing the following value to TWCR:  
TWCR  
TWINT  
TWEA  
TWSTA  
TWSTO  
TWWC  
TWEN  
TWIE  
value  
1
X
1
0
X
1
0
X
214  
ATmega48/88/168  
2545D–AVR–07/04  
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