ATmega48/88/168
Timer/Counter1 – TCNT1H
and TCNT1L
Bit
7
6
5
4
3
2
1
0
TCNT1[15:8]
TCNT1[7:0]
TCNT1H
TCNT1L
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit tempo-
rary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 106.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing
a compare match between TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following
timer clock for all compare units.
Output Compare Register 1 A
– OCR1AH and OCR1AL
Bit
7
6
5
4
3
2
1
0
OCR1A[15:8]
OCR1A[7:0]
OCR1AH
OCR1AL
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
Output Compare Register 1 B
– OCR1BH and OCR1BL
Bit
7
6
5
4
3
2
1
0
OCR1B[15:8]
OCR1B[7:0]
OCR1BH
OCR1BL
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
The Output Compare Registers contain a 16-bit value that is continuously compared
with the counter value (TCNT1). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low
bytes are written simultaneously when the CPU writes to these registers, the access is
performed using an 8-bit temporary High Byte Register (TEMP). This temporary register
is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 106.
Input Capture Register 1 –
ICR1H and ICR1L
Bit
7
6
5
4
3
2
1
0
ICR1[15:8]
ICR1[7:0]
ICR1H
ICR1L
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
0
The Input Capture is updated with the counter (TCNT1) value each time an event occurs
on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1).
The Input Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes
are read simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary High Byte Register (TEMP). This temporary register is
shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 106.
129
2545D–AVR–07/04
ATMEL [ ATMEL ]
