ATmega48/88/168
the edge detector uses sampling, the maximum frequency of an external clock it can
detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-
ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,
resonator, and capacitors) tolerances, it is recommended that maximum frequency of an
external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 40. Prescaler for Timer/Counter0 and Timer/Counter1(1)
clkI/O
Clear
PSRSYNC
T0
Synchronization
T1
Synchronization
clkT1
clkT0
Note:
1. The synchronization logic on the input pins (T1/T0) is shown in Figure 39.
General Timer/Counter
Control Register – GTCCR
Bit
7
6
–
5
–
4
–
3
–
2
–
1
PSRASY
R/W
0
PSRSYNC
R/W
TSM
R/W
0
GTCCR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
0
0
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this
mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keep-
ing the corresponding prescaler reset signals asserted. This ensures that the
corresponding Timer/Counters are halted and can be configured to the same value with-
out the risk of one of them advancing during configuration. When the TSM bit is written
to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the
Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This
bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that
Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this pres-
caler will affect both timers.
103
2545D–AVR–07/04
ATMEL [ ATMEL ]
