Table 112. Parallel Programming Characteristics, VCC = 5 V 10ꢀ (Continued)
Symbol
tBVDV
Parameter
Min
Typ
Max
250
250
250
Units
ns
BS1 Valid to DATA valid
OE Low to DATA Valid
OE High to DATA Tri-stated
0
tOLDV
ns
tOHDZ
ns
Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock
bits commands.
2. tWLRH_CE is valid for the Chip Erase command.
SPI Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI
bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI
(input), and MISO (output). After RESET is set low, the Programming Enable instruction
needs to be executed first before program/erase operations can be executed. NOTE, in
Table 113 on page 270, the pin mapping for SPI programming is listed. Not all parts use
the SPI pins dedicated for the internal SPI interface.
SPI Serial Programming
Pin Mapping
Table 113. Pin Mapping SPI Serial Programming
Symbol
MOSI
MISO
SCK
Pins
PB5
PB6
PB7
I/O
Description
Serial Data in
Serial Data out
Serial Clock
I
O
I
Figure 136. SPI Serial Programming and Verify(1)
+2.7 - 5.5V
VCC
+2.7 - 5.5V(2)
PB5
PB6
PB7
MOSI
MISO
AVCC
SCK
XTAL1
RESET
GND
Notes: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock
source to the XTAL1 pin.
2. VCC -0.3V < AVCC < VCC +0.3V, however, AVCC should always be within 2.7 - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-
gramming operation (in the serial mode ONLY) and there is no need to first execute the
270
ATmega32(L)
2503J–AVR–10/06
ATMEL [ ATMEL ]
