Parallel Programming
Characteristics
Figure 133. Parallel Programming Timing, Including some General Timing
Requirements
tXLWL
tXHXL
XTAL1
tDVXH
tXLDX
Data & Contol
(DATA, XA0/1, BS1, BS2)
tBVPH
tPLBX
t BVWL
tWLBX
PAGEL
tPHPL
tWL WH
WR
tPLWL
WLRL
RDY/BSY
tWLRH
Figure 134. Parallel Programming Timing, Loading Sequence with Timing
Requirements(1)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
tXLPH
tXLXH
tPLXH
XTAL1
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. The timing requirements shown in Figure 133 (i.e., tDVXH, tXHXL, and tXLDX) also apply
to loading operation.
268
ATmega32(L)
2503J–AVR–10/06