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ATMEGA32L-8AUR 参数 Datasheet PDF下载

ATMEGA32L-8AUR图片预览
型号: ATMEGA32L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
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ATmega32(L)  
Table 103. Lock Bit Protection Modes (Continued)  
Memory Lock Bits(2)  
Protection Type  
No restrictions for SPM or LPM accessing the Boot Loader  
section.  
1
2
1
1
1
0
SPM is not allowed to write to the Boot Loader section.  
SPM is not allowed to write to the Boot Loader section,  
and LPM executing from the Application section is not  
allowed to read from the Boot Loader section. If interrupt  
vectors are placed in the Application section, interrupts  
are disabled while executing from the Boot Loader section.  
3
0
0
LPM executing from the Application section is not allowed  
to read from the Boot Loader section. If interrupt vectors  
are placed in the Application section, interrupts are  
disabled while executing from the Boot Loader section.  
4
0
1
Notes: 1. Program the fuse bits before programming the Lock bits.  
2. “1” means unprogrammed, “0” means programmed  
Fuse Bits  
The ATmega32 has two fuse bytes. Table 104 and Table 105 describe briefly the func-  
tionality of all the fuses and how they are mapped into the fuse bytes. Note that the  
fuses are read as logical zero, “0”, if they are programmed.  
Table 104. Fuse High Byte  
FuseHigh  
Byte  
Bit  
No.  
Description  
Enable OCD  
Enable JTAG  
Default Value  
OCDEN(4)  
JTAGEN(5)  
7
6
1 (unprogrammed, OCD disabled)  
0 (programmed, JTAG enabled)  
Enable SPI Serial Program and  
Data Downloading  
SPIEN(1)  
CKOPT(2)  
EESAVE  
5
4
3
0 (programmed, SPI prog. enabled)  
1 (unprogrammed)  
Oscillator options  
EEPROM memory is preserved  
through the Chip Erase  
1 (unprogrammed, EEPROM not  
preserved)  
Select Boot Size (see Table 99  
for details)  
BOOTSZ1  
2
0 (programmed)(3)  
Select Boot Size (see Table 99  
for details)  
BOOTSZ0  
BOOTRST  
1
0
0 (programmed)(3)  
1 (unprogrammed)  
Select reset vector  
Notes: 1. The SPIEN Fuse is not accessible in SPI Serial Programming mode.  
2. The CKOPT Fuse functionality depends on the setting of the CKSEL bits. See See  
“Clock Sources” on page 25. for details.  
3. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 99 on  
page 255.  
4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of  
Lock bits and the JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of  
the clock system to be running in all sleep modes. This may increase the power  
consumption.  
5. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be dis-  
abled. This to avoid static current at the TDO pin in the JTAG interface.  
257  
2503J–AVR–10/06  
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