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ATMEGA32L-8AUR 参数 Datasheet PDF下载

ATMEGA32L-8AUR图片预览
型号: ATMEGA32L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
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ATmega32(L)  
as for board level systems using the Flash, and the same design solutions should be  
applied.  
A Flash program corruption can be caused by two situations when the voltage is too low.  
First, a regular write sequence to the Flash requires a minimum voltage to operate  
correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply  
voltage for executing instructions is too low.  
Flash corruption can easily be avoided by following these design recommendations (one  
is sufficient):  
1. If there is no need for a Boot Loader update in the system, program the Boot  
Loader Lock bits to prevent any Boot Loader software updates.  
2. Keep the AVR RESET active (low) during periods of insufficient power supply  
voltage. This can be done by enabling the internal Brown-out Detector (BOD) if  
the operating voltage matches the detection level. If not, an external low VCC  
Reset Protection circuit can be used. If a reset occurs while a write operation is  
in progress, the write operation will be completed provided that the power supply  
voltage is sufficient.  
3. Keep the AVR core in Power-down Sleep mode during periods of low VCC. This  
will prevent the CPU from attempting to decode and execute instructions, effec-  
tively protecting the SPMCR Register and thus the Flash from unintentional  
writes.  
Programming Time for Flash  
when using SPM  
The Calibrated RC Oscillator is used to time Flash accesses. Table 98 shows the typical  
programming time for Flash accesses from the CPU.  
Table 98. SPM Programming Time.  
Symbol  
Min Programming Time  
Max Programming Time  
Flash write (Page Erase, Page  
Write, and write Lock bits by SPM)  
3.7 ms  
4.5 ms  
Simple Assembly Code  
Example for a Boot Loader  
;-the routine writes one page of data from RAM to Flash  
; the first data location in RAM is pointed to by the Y pointer  
; the first data location in Flash is pointed to by the Z pointer  
;-error handling is not included  
;-the routine must be placed inside the boot space  
; (at least the Do_spm sub routine). Only code inside NRWW section can  
; be read during self-programming (page erase and page write).  
;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),  
; loophi (r25), spmcrval (r20)  
; storing and restoring of registers is not included in the routine  
; register usage can be optimized at the expense of code size  
;-It is assumed that either the interrupt table is moved to the Boot  
; loader section or that the interrupts are disabled.  
.equ PAGESIZEB = PAGESIZE*2  
; PAGESIZEB is page size in BYTES, not  
; words  
.org SMALLBOOTSTART  
Write_page:  
; page erase  
ldi  
spmcrval, (1<<PGERS) | (1<<SPMEN)  
call Do_spm  
; re-enable the RWW section  
ldi  
spmcrval, (1<<RWWSRE) | (1<<SPMEN)  
call Do_spm  
; transfer data from RAM to Flash page buffer  
ldi looplo, low(PAGESIZEB) ;init loop variable  
253  
2503J–AVR–10/06  
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