The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –
which is not provided.
When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins
and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is
cleared, the TAP input signals are internally pulled high and the JTAG is enabled for
Boundary-scan and programming. In this case, the TAP output pin (TDO) is left floating
in states where the JTAG TAP controller is not shifting data, and must therefore be con-
nected to a pull-up resistor or other hardware having pull-ups (for instance the TDI-input
of the next device in the scan chain). The device is shipped with this fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is
monitored by the debugger to be able to detect external reset sources. The debuggerbta
can also pull the RESET pin low to reset the whole system, assuming only open collec-
tors on the reset line are used in the application.
Figure 112. Block Diagram
I/O PORT 0
DEVICE BOUNDARY
BOUNDARY SCAN CHAIN
TDI
JTAG PROGRAMMING
TDO
TAP
INTERFACE
TCK
TMS
CONTROLLER
AVR CPU
INTERNAL
SCAN
CHAIN
FLASH
MEMORY
Address
Data
PC
Instruction
INSTRUCTION
REGISTER
ID
REGISTER
BREAKPOINT
UNIT
M
U
X
FLOW CONTROL
UNIT
BYPASS
REGISTER
DIGITAL
PERIPHERAL
UNITS
BREAKPOINT
SCAN CHAIN
JTAG / AVR CORE
COMMUNICATION
INTERFACE
ADDRESS
DECODER
OCD STATUS
AND CONTROL
I/O PORT n
220
ATmega32(L)
2503J–AVR–10/06
ATMEL [ ATMEL ]
