Figure 98. Analog to Digital Converter Block Schematic
ADC CONVERSION
COMPLETE IRQ
INTERRUPT
FLAGS
ADTS[2:0]
8-BIT DATA BUS
15
0
ADC MULTIPLEXER
SELECT (ADMUX)
ADC CTRL. & STATUS
REGISTER (ADCSRA)
ADC DATA REGISTER
(ADCH/ADCL)
TRIGGER
SELECT
MUX DECODER
PRESCALER
START
CONVERSION LOGIC
AVCC
INTERNAL 2.56V
REFERENCE
SAMPLE & HOLD
COMPARATOR
AREF
GND
10-BIT DAC
-
+
BANDGAP
REFERENCE
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
SINGLE ENDED / DIFFERENTIAL SELECTION
POS.
INPUT
MUX
ADC MULTIPLEXER
OUTPUT
GAIN
AMPLIFIER
+
-
NEG.
INPUT
MUX
Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive
approximation. The minimum value represents GND and the maximum value represents
the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V refer-
ence voltage may be connected to the AREF pin by writing to the REFSn bits in the
ADMUX Register. The internal voltage reference may thus be decoupled by an external
capacitor at the AREF pin to improve noise immunity.
The analog input channel and differential gain are selected by writing to the MUX bits in
ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage refer-
ence, can be selected as single ended inputs to the ADC. A selection of ADC input pins
can be selected as positive and negative inputs to the differential gain amplifier.
If differential channels are selected, the differential gain stage amplifies the voltage dif-
ference between the selected input channel pair by the selected gain factor. This
202
ATmega32(L)
2503J–AVR–10/06
ATMEL [ ATMEL ]
