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ATMEGA32L-8AUR 参数 Datasheet PDF下载

ATMEGA32L-8AUR图片预览
型号: ATMEGA32L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
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ATmega32(L)  
Analog to Digital  
Converter  
Features  
10-bit Resolution  
0.5 LSB Integral Non-linearity  
2 LSB Absolute Accuracy  
13 - 260 µs Conversion Time  
Up to 15 kSPS at Maximum Resolution  
8 Multiplexed Single Ended Input Channels  
7 Differential Input Channels  
2 Differential Input Channels with Optional Gain of 10x and 200x(1)  
Optional Left adjustment for ADC Result Readout  
0 - VCC ADC Input Voltage Range  
Selectable 2.56V ADC Reference Voltage  
Free Running or Single Conversion Mode  
ADC Start Conversion by Auto Triggering on Interrupt Sources  
Interrupt on ADC Conversion Complete  
Sleep Mode Noise Canceler  
Note:  
1. The differential input channels are not tested for devices in PDIP Package. This fea-  
ture is only guaranteed to work for devices in TQFP and QFN/MLF Packages  
The ATmega32 features a 10-bit successive approximation ADC. The ADC is con-  
nected to an 8-channel Analog Multiplexer which allows 8 single-ended voltage inputs  
constructed from the pins of Port A. The single-ended voltage inputs refer to 0V (GND).  
The device also supports 16 differential voltage input combinations. Two of the differen-  
tial inputs (ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain  
stage, providing amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the dif-  
ferential input voltage before the A/D conversion. Seven differential analog input  
channels share a common negative terminal (ADC1), while any other ADC input can be  
selected as the positive input terminal. If 1x or 10x gain is used, 8-bit resolution can be  
expected. If 200x gain is used, 7-bit resolution can be expected.  
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the  
ADC is held at a constant level during conversion. A block diagram of the ADC is shown  
in Figure 98.  
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more  
than 0.3 V from VCC. See the paragraph “ADC Noise Canceler” on page 209 on how to  
connect this pin.  
Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The volt-  
age reference may be externally decoupled at the AREF pin by a capacitor for better  
noise performance.  
201  
2503J–AVR–10/06  
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