When OC2 is connected to the pin, the function of the COM21:0 bits depends on the
WGM21:0 bit setting. Table 51 shows the COM21:0 bit functionality when the WGM21:0
bits are set to a normal or CTC mode (non-PWM).
Table 51. Compare Output Mode, non-PWM Mode
COM21
COM20
Description
0
0
1
1
0
1
0
1
Normal port operation, OC2 disconnected.
Toggle OC2 on compare match
Clear OC2 on compare match
Set OC2 on compare match
Table 52 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast
PWM mode.
Table 52. Compare Output Mode, Fast PWM Mode(1)
COM21
COM20
Description
0
0
1
0
1
0
Normal port operation, OC2 disconnected.
Reserved
Clear OC2 on compare match, set OC2 at BOTTOM,
(non-inverting mode)
1
1
Set OC2 on compare match, clear OC2 at BOTTOM,
(inverting mode)
Note:
1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the
compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode”
on page 120 for more details.
Table 53 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase
correct PWM mode
.
Table 53. Compare Output Mode, Phase Correct PWM Mode(1)
COM21 COM20 Description
0
0
1
0
1
0
Normal port operation, OC2 disconnected.
Reserved
Clear OC2 on compare match when up-counting. Set OC2 on compare
match when downcounting.
1
1
Set OC2 on compare match when up-counting. Clear OC2 on compare
match when downcounting.
Note:
1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the
compare match is ignored, but the set or clear is done at TOP. See “Phase Correct
PWM Mode” on page 121 for more details.
126
ATmega32(L)
2503J–AVR–10/06
ATMEL [ ATMEL ]
