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ATMEGA32L-8AUR 参数 Datasheet PDF下载

ATMEGA32L-8AUR图片预览
型号: ATMEGA32L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
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AsynchronousOperation  
of the Timer/Counter  
Asynchronous Status  
Register – ASSR  
Bit  
7
6
5
4
3
2
1
0
AS2  
R/W  
0
TCN2UB  
OCR2UB  
TCR2UB  
ASSR  
Read/Write  
Initial Value  
R
0
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 3 – AS2: Asynchronous Timer/Counter2  
When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clkI/O. When  
AS2 is written to one, Timer/Counter2 is clocked from a Crystal Oscillator connected to  
the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of  
TCNT2, OCR2, and TCCR2 might be corrupted.  
• Bit 2 – TCN2UB: Timer/Counter2 Update Busy  
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes  
set. When TCNT2 has been updated from the temporary storage register, this bit is  
cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be  
updated with a new value.  
• Bit 1 – OCR2UB: Output Compare Register2 Update Busy  
When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes  
set. When OCR2 has been updated from the temporary storage register, this bit is  
cleared by hardware. A logical zero in this bit indicates that OCR2 is ready to be  
updated with a new value.  
• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy  
When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes  
set. When TCCR2 has been updated from the temporary storage register, this bit is  
cleared by hardware. A logical zero in this bit indicates that TCCR2 is ready to be  
updated with a new value.  
If a write is performed to any of the three Timer/Counter2 Registers while its update  
busy flag is set, the updated value might get corrupted and cause an unintentional inter-  
rupt to occur.  
The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading  
TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the  
temporary storage register is read.  
Asynchronous Operation of  
Timer/Counter2  
When Timer/Counter2 operates asynchronously, some considerations must be taken.  
Warning: When switching between asynchronous and synchronous clocking of  
Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be  
corrupted. A safe procedure for switching clock source is:  
1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2.  
2. Select clock source by setting AS2 as appropriate.  
3. Write new values to TCNT2, OCR2, and TCCR2.  
4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and  
TCR2UB.  
5. Clear the Timer/Counter2 Interrupt Flags.  
128  
ATmega32(L)  
2503J–AVR–10/06  
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