ATmega32(L)
•
The timer starts counting from a value higher than the one in OCR2A, and for that
reason misses the Compare Match and hence the OCn change that would have
happened on the way up.
Timer/Counter Timing
Diagrams
The following figures show the Timer/Counter in Synchronous mode, and the timer clock
(clkT2) is therefore shown as a clock enable signal. In Asynchronous mode, clkI/O should
be replaced by the Timer/Counter Oscillator clock. The figures include information on
when Interrupt Flags are set. Figure 60 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.
Figure 60. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O/1)
TCNTn
TOVn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
Figure 61 shows the same timing data, but with the prescaler enabled.
Figure 61. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
TOVn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
Figure 62 shows the setting of OCF2 in all modes except CTC mode.
123
2503J–AVR–10/06
ATMEL [ ATMEL ]
