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ATMEGA2560 参数 Datasheet PDF下载

ATMEGA2560图片预览
型号: ATMEGA2560
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器与256K字节的系统内可编程闪存 [8- BIT Microcontroller with 256K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 407 页 / 2985 K
品牌: ATMEL [ ATMEL ]
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ATmega640/1280/1281/2560/2561  
Table 151. Fuse High Byte  
Fuse High Byte Bit No Description  
Default Value  
1 (unprogrammed, OCD  
disabled)  
OCDEN(4)  
7
6
Enable OCD  
0 (programmed, JTAG  
enabled)  
JTAGEN  
Enable JTAG  
Enable Serial Program and Data  
Downloading  
0 (programmed, SPI prog.  
enabled)  
SPIEN(1)  
WDTON(3)  
EESAVE  
5
4
3
Watchdog Timer always on  
1 (unprogrammed)  
EEPROM memory is preserved  
through the Chip Erase  
1 (unprogrammed,  
EEPROM not preserved)  
Select Boot Size (see Table 153  
for details)  
BOOTSZ1  
2
0 (programmed)(2)  
Select Boot Size (see Table 153  
for details)  
BOOTSZ0  
BOOTRST  
1
0
0 (programmed)(2)  
1 (unprogrammed)  
Select Reset Vector  
Note:  
1. The SPIEN Fuse is not accessible in serial programming mode.  
2. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 139 on  
page 330 for details.  
3. See “Watchdog Timer Control Register - WDTCSR” on page 67 for details.  
4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of  
Lock bits and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the  
clock system to be running in all sleep modes. This may increase the power  
consumption.  
Table 152. Fuse Low Byte  
Fuse Low Byte  
CKDIV8(4)  
CKOUT(3)  
SUT1  
Bit No  
Description  
Default Value  
7
6
5
4
3
2
1
0
Divide clock by 8  
Clock output  
0 (programmed)  
1 (unprogrammed)  
1 (unprogrammed)(1)  
0 (programmed)(1)  
0 (programmed)(2)  
0 (programmed)(2)  
1 (unprogrammed)(2)  
0 (programmed)(2)  
Select start-up time  
Select start-up time  
Select Clock source  
Select Clock source  
Select Clock source  
Select Clock source  
SUT0  
CKSEL3  
CKSEL2  
CKSEL1  
CKSEL0  
Note:  
1. The default value of SUT1..0 results in maximum start-up time for the default clock  
source. See Table 23 on page 58 for details.  
2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See  
Table 7 on page 40 for details.  
3. The CKOUT Fuse allow the system clock to be output on PORTE7. See “Clock Out-  
put Buffer” on page 48 for details.  
4. See “System Clock Prescaler” on page 48 for details.  
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are  
locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the  
Lock bits.  
337  
2549A–AVR–03/05  
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