• Bit 5:3 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future
devices, these bits must be written to zero when UCSRnC is written.
• Bit 2 - UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB
of the data word is transmitted first. Refer to the Frame Formats section page 4 for
details.
• Bit 1 - UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing
(last) edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 - UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn
and UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data
Modes and Timing section page 4 for details.
USART MSPIM Baud Rate
Registers - UBRRnL and
UBRRnH
The function and bit description of the baud rate registers in MSPI mode is identical to
normal USART operation. See “USART Baud Rate Registers – UBRRLn and UBRRHn”
on page 226.
AVR USART MSPIM vs.
AVR SPI
The USART in MSPIM mode is fully compatible with the AVR SPI regarding:
•
•
•
•
Master mode timing diagram.
The UCPOLn bit functionality is identical to the SPI CPOL bit.
The UCPHAn bit functionality is identical to the SPI CPHA bit.
The UDORDn bit functionality is identical to the SPI DORD bit.
However, since the USART in MSPIM mode reuses the USART resources, the use of
the USART in MSPIM mode is somewhat different compared to the SPI. In addition to
differences of the control register bits, and that only master operation is supported by
the USART in MSPIM mode, the following features differ between the two modules:
•
The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI
has no buffer.
•
•
•
The USART in MSPIM mode receiver includes an additional buffer level.
The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode.
The SPI double speed mode (SPI2X) bit is not included. However, the same effect is
achieved by setting UBRRn accordingly.
•
•
Interrupt timing is not compatible.
Pin control differs due to the master only operation of the USART in MSPIM mode.
A comparison of the USART in MSPIM mode and the SPI pins is shown in Table 113 on
page 239.
238
ATmega640/1280/1281/2560/2561
2549A–AVR–03/05
ATMEL [ ATMEL ]
