ATmega640/1280/1281/2560/2561
2-wire Serial Interface
Features
• Simple yet Powerful and Flexible Communication Interface, only two Bus Lines needed
• Both Master and Slave Operation Supported
• Device can Operate as Transmitter or Receiver
• 7-bit Address Space Allows up to 128 Different Slave Addresses
• Multi-master Arbitration Support
• Up to 400 kHz Data Transfer Speed
• Slew-rate Limited Output Drivers
• Noise Suppression Circuitry Rejects Spikes on Bus Lines
• Fully Programmable Slave Address with General Call Support
• Address Recognition Causes Wake-up When AVR is in Sleep Mode
2-wire Serial Interface
Bus Definition
The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications.
The TWI protocol allows the systems designer to interconnect up to 128 different
devices using only two bi-directional bus lines, one for clock (SCL) and one for data
(SDA). The only external hardware needed to implement the bus is a single pull-up
resistor for each of the TWI bus lines. All devices connected to the bus have individual
addresses, and mechanisms for resolving bus contention are inherent in the TWI
protocol.
Figure 91. TWI Bus Interconnection
VCC
Device 1
Device 3
R1
R2
Device 2
Device n
........
SDA
SCL
TWI Terminology
The following definitions are frequently encountered in this section.
Table 114. TWI Terminology
Term
Description
Master
The device that initiates and terminates a transmission. The Master also
generates the SCL clock.
Slave
The device addressed by a Master.
The device placing data on the bus.
The device reading data from the bus.
Transmitter
Receiver
The Power Reduction TWI bit, PRTWI bit in “Power Reduction Register 0 - PRR0” on
page 54 must be written to zero to enable the 2-wire Serial Interface.
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2549A–AVR–03/05
ATMEL [ ATMEL ]
