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ATMEGA2560 参数 Datasheet PDF下载

ATMEGA2560图片预览
型号: ATMEGA2560
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器与256K字节的系统内可编程闪存 [8- BIT Microcontroller with 256K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 407 页 / 2985 K
品牌: ATMEL [ ATMEL ]
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Assembly Code Example(1)  
USART_Init:  
clr r18  
out UBRRnH,r18  
out UBRRnL,r18  
; Setting the XCKn port pin as output, enables master mode.  
sbi XCKn_DDR, XCKn  
; Set MSPI mode of operation and SPI data mode 0.  
ldi r18, (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn)  
out UCSRnC,r18  
; Enable receiver and transmitter.  
ldi r18, (1<<RXENn)|(1<<TXENn)  
out UCSRnB,r18  
; Set baud rate.  
; IMPORTANT: The Baud Rate must be set after the transmitter is enabled!  
out UBRRnH, r17  
out UBRRnL, r18  
ret  
C Code Example(1)  
void USART_Init( unsigned int baud )  
{
UBRRn = 0;  
/* Setting the XCKn port pin as output, enables master mode. */  
XCKn_DDR |= (1<<XCKn);  
/* Set MSPI mode of operation and SPI data mode 0. */  
UCSRnC = (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn);  
/* Enable receiver and transmitter. */  
UCSRnB = (1<<RXENn)|(1<<TXENn);  
/* Set baud rate. */  
/* IMPORTANT: The Baud Rate must be set after the transmitter is enabled  
*/  
UBRRn = baud;  
}
Note:  
1. See “About Code Examples” on page 8.  
Data Transfer  
Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn  
bit in the UCSRnB register is set to one. When the Transmitter is enabled, the normal  
port operation of the TxDn pin is overridden and given the function as the Transmitter's  
serial output. Enabling the receiver is optional and is done by setting the RXENn bit in  
the UCSRnB register to one. When the receiver is enabled, the normal pin operation of  
the RxDn pin is overridden and given the function as the Receiver's serial input. The  
XCKn will in both cases be used as the transfer clock.  
After initialization the USART is ready for doing data transfers. A data transfer is initiated  
by writing to the UDRn I/O location. This is the case for both sending and receiving data  
since the transmitter controls the transfer clock. The data written to UDRn is moved from  
234  
ATmega640/1280/1281/2560/2561  
2549A–AVR–03/05  
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