ATmega640/1280/1281/2560/2561
do not contain data to be transmitted. When disabled, the Transmitter will no longer
override the TxDn port.
• Bit 2 – UCSZn2: Character Size n
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data
bits (Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8 n
RXB8n is the ninth data bit of the received character when operating with serial frames
with nine data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8 n
TXB8n is the ninth data bit in the character to be transmitted when operating with serial
frames with nine data bits. Must be written before writing the low bits to UDRn.
USART Control and Status
Register n C – UCSRnC
Bit
7
UMSELn1
R/W
6
UMSELn0
R/W
5
UPMn1
R/W
0
4
UPMn0
R/W
0
3
USBSn
R/W
0
2
UCSZn1
R/W
1
UCSZn0
R/W
0
UCPOLn
R/W
UCSRnC
Read/Write
Initial Value
0
0
1
1
0
• Bits 7:6 – UMSELn1:0 USART Mode Select
These bits select the mode of operation of the USARTn as shown in Table 101..
Table 101. UMSELn Bits Settings
UMSELn1
UMSELn0
Mode
0
0
1
1
0
1
0
1
Asynchronous USART
Synchronous USART
(Reserved)
Master SPI (MSPIM)(1)
Note:
1. See “USART in SPI Mode” on page 231 for full description of the Master SPI Mode
(MSPIM) operation
• Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmit-
ter will automatically generate and send the parity of the transmitted data bits within
each frame. The Receiver will generate a parity value for the incoming data and com-
pare it to the UPMn setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be
set.
Table 102. UPMn Bits Settings
UPMn1
UPMn0
Parity Mode
0
0
1
1
0
1
0
1
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
225
2549A–AVR–03/05
ATMEL [ ATMEL ]
