• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver
ignores this setting.
Table 103. USBS Bit Settings
USBSn
Stop Bit(s)
1-bit
0
1
2-bit
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data
bits (Character SiZe) in a frame the Receiver and Transmitter use.
Table 104. UCSZn Bits Settings
UCSZn2
UCSZn1
UCSZn0
Character Size
5-bit
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous
mode is used. The UCPOLn bit sets the relationship between data output change and
data input sample, and the synchronous clock (XCKn).
Table 105. UCPOLn Bit Settings
Transmitted Data Changed (Output
of TxDn Pin)
Received Data Sampled (Input on
RxDn Pin)
UCPOLn
0
1
Rising XCKn Edge
Falling XCKn Edge
Falling XCKn Edge
Rising XCKn Edge
USART Baud Rate Registers –
UBRRLn and UBRRHn
Bit
15
14
13
12
11
10
9
8
–
–
–
–
UBRR[11:8]
UBRRHn
UBRRLn
UBRR[7:0]
7
R
6
R
5
R
4
R
3
R/W
R/W
0
2
R/W
R/W
0
1
R/W
R/W
0
0
R/W
R/W
0
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
0
0
0
0
0
0
0
0
226
ATmega640/1280/1281/2560/2561
2549A–AVR–03/05
ATMEL [ ATMEL ]
