ATmega640/1280/1281/2560/2561
Serial Peripheral
Interface – SPI
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the ATmega640/1280/1281/2560/2561 and peripheral devices or between sev-
eral AVR devices. The ATmega640/1280/1281/2560/2561 SPI includes the following
features:
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 231.
The Power Reduction SPI bit, PRSPI, in “Power Reduction Register 0 - PRR0” on page
54 on page 50 must be written to zero to enable SPI module.
Figure 79. SPI Block Diagram(1)
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Note:
1. Refer to Figure 1 on page 2, and Table 39 on page 89 for SPI pin placement.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 80.
The system consists of two shift Registers, and a Master clock generator. The SPI Mas-
ter initiates the communication cycle when pulling low the Slave Select SS pin of the
desired Slave. Master and Slave prepare the data to be sent in their respective shift
Registers, and the Master generates the required clock pulses on the SCK line to inter-
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ATMEL [ ATMEL ]
