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ATMEGA2560 参数 Datasheet PDF下载

ATMEGA2560图片预览
型号: ATMEGA2560
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器与256K字节的系统内可编程闪存 [8- BIT Microcontroller with 256K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 407 页 / 2985 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA2560的Datasheet PDF文件第188页浏览型号ATMEGA2560的Datasheet PDF文件第189页浏览型号ATMEGA2560的Datasheet PDF文件第190页浏览型号ATMEGA2560的Datasheet PDF文件第191页浏览型号ATMEGA2560的Datasheet PDF文件第193页浏览型号ATMEGA2560的Datasheet PDF文件第194页浏览型号ATMEGA2560的Datasheet PDF文件第195页浏览型号ATMEGA2560的Datasheet PDF文件第196页  
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable  
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the  
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if  
an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the  
Timer/Counter2 Interrupt Flag Register – TIFR2.  
Timer/Counter2 Interrupt Flag  
Register – TIFR2  
Bit  
7
6
5
4
3
2
OCF2B  
R/W  
0
1
OCF2A  
R/W  
0
0
TOV2  
R/W  
0
TIFR2  
Read/Write  
Initial Value  
R
0
R
0
R
0
R
0
R
0
• Bit 2 – OCF2B: Output Compare Flag 2 B  
The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2  
and the data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware  
when executing the corresponding interrupt handling vector. Alternatively, OCF2B is  
cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B  
(Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the  
Timer/Counter2 Compare match Interrupt is executed.  
• Bit 1 – OCF2A: Output Compare Flag 2 A  
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2  
and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware  
when executing the corresponding interrupt handling vector. Alternatively, OCF2A is  
cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A  
(Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the  
Timer/Counter2 Compare match Interrupt is executed.  
• Bit 0 – TOV2: Timer/Counter2 Overflow Flag  
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared  
by hardware when executing the corresponding interrupt handling vector. Alternatively,  
TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A  
(Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the  
Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when  
Timer/Counter2 changes counting direction at 0x00.  
192  
ATmega640/1280/1281/2560/2561  
2549A–AVR–03/05  
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