than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since
the edge detector uses sampling, the maximum frequency of an external clock it can
detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-
ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,
resonator, and capacitors) tolerances, it is recommended that maximum frequency of an
external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 39. Prescaler for Timer/Counter0 and Timer/Counter1(1)
clkI/O
Clear
PSR10
T0
Synchronization
T1
Synchronization
clkT1
clkT0
Note:
1. The synchronization logic on the input pins (T1/T0) is shown in Figure 38.
Special Function IO Register –
SFIOR
Bit
7
ADTS2
R/W
0
6
ADTS1
R/W
0
5
ADTS0
R/W
0
4
ADHSM
R/W
0
3
ACME
R/W
0
2
1
PSR2
R/W
0
0
PSR10
R/W
0
PUD
R/W
0
SFIOR
Read/Write
Initial Value
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be
reset. The bit will be cleared by hardware after the operation is performed. Writing a
zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share
the same prescaler and a reset of this prescaler will affect both timers. This bit will
always be read as zero.
82
ATmega16(L)
2466E–AVR–10/02
ATMEL [ ATMEL ]
