ATmega16(L)
Figure 37 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.
Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with
Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
(CTC)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
OCRn
TOP
OCFn
8-bit Timer/Counter
Register Description
Timer/Counter Control
Register – TCCR0
Bit
7
FOC0
W
6
WGM00
R/W
0
5
COM01
R/W
0
4
COM00
R/W
0
3
WGM01
R/W
0
2
1
CS01
R/W
0
0
CS02
R/W
0
CS00
R/W
0
TCCR0
Read/Write
Initial Value
0
• Bit 7 – FOC0: Force Output Compare
The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However,
for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is
written when operating in PWM mode. When writing a logical one to the FOC0 bit, an
immediate compare match is forced on the Waveform Generation unit. The OC0 output
is changed according to its COM01:0 bits setting. Note that the FOC0 bit is implemented
as a strobe. Therefore it is the value present in the COM01:0 bits that determines the
effect of the forced compare.
A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode
using OCR0 as TOP.
The FOC0 bit is always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum
(TOP) counter value, and what type of Waveform Generation to be used. Modes of
operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Com-
pare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See
Table 38 and “Modes of Operation” on page 71.
77
2466E–AVR–10/02
ATMEL [ ATMEL ]
