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ATMEGA16U2-MUR 参数 Datasheet PDF下载

ATMEGA16U2-MUR图片预览
型号: ATMEGA16U2-MUR
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有ISP功能的Flash 8/16 / 32K Butes [8-bit Microcontroller with 8/16/32K Butes of ISP Flash]
分类和应用: 微控制器异步传输模式PCATM
文件页数/大小: 310 页 / 4432 K
品牌: ATMEL [ ATMEL ]
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ATmega8U2/16U2/32U2  
12.2.6  
Unconnected Pins  
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even  
though most of the digital inputs are disabled in the deep sleep modes as described above, float-  
ing inputs should be avoided to reduce current consumption in all other modes where the digital  
inputs are enabled (Reset, Active mode and Idle mode).  
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.  
In this case, the pull-up will be disabled during reset. If low power consumption during reset is  
important, it is recommended to use an external pull-up or pull-down. Connecting unused pins  
directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is  
accidentally configured as an output.  
12.3 Alternate Port Functions  
Most port pins have alternate functions in addition to being general digital I/Os. Figure 12-5  
shows how the port pin control signals from the simplified Figure 12-2 can be overridden by  
alternate functions. The overriding signals may not be present in all port pins, but the figure  
serves as a generic description applicable to all port pins in the AVR microcontroller family.  
Figure 12-5. Alternate Port Functions(1)  
PUOExn  
PUOVxn  
1
PUD  
0
DDOExn  
DDOVxn  
1
Q
D
0
DDxn  
Q CLR  
WDx  
RDx  
PVOExn  
PVOVxn  
RESET  
1
0
1
0
Pxn  
Q
D
PORTxn  
PTOExn  
Q CLR  
DIEOExn  
DIEOVxn  
SLEEP  
WPx  
RESET  
WRx  
1
0
RRx  
SYNCHRONIZER  
RPx  
SET  
D
Q
D
L
Q
Q
PINxn  
CLR Q  
CLR  
clk I/O  
DIxn  
AIOxn  
PUOExn: Pxn PULL-UP OVERRIDE ENABLE  
PUOVxn: Pxn PULL-UP OVERRIDE VALUE  
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE  
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE  
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE  
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE  
PUD:  
WDx:  
RDx:  
RRx:  
WRx:  
RPx:  
WPx:  
PULLUP DISABLE  
WRITE DDRx  
READ DDRx  
READ PORTx REGISTER  
WRITE PORTx  
READ PORTx PIN  
WRITE PINx  
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE  
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE  
clkI/O  
:
I/O CLOCK  
SLEEP:  
SLEEP CONTROL  
DIxn:  
DIGITAL INPUT PIN n ON PORTx  
AIOxn:  
ANALOG INPUT/OUTPUT PIN n ON PORTx  
PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE  
72  
7799D–AVR–11/10