ATmega8U2/16U2/32U2
.Table 12-4 and Table 12-5 relate the alternate functions of Port B to the overriding signals
shown in Figure 12-5 on page 72. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT..
Table 12-4. Overriding Signals for Alternate Functions in PB7..PB4
Signal
Name
PB7/OC0A/OC1C/
PCINT7
PB6/PCINT6
PB5/PCINT5
PB4/T1/PCINT4
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OC0A/OC1C ENABLE
OC0A/OC1C
PCINT7 • PCIE0
1
0
0
0
0
0
0
PCINT6 • PCIE0
1
PCINT5 • PCIE0
1
PCINT4 • PCIE0
1
PCINT4 INPUT
T1 INPUT
DI
PCINT7 INPUT
–
PCINT6 INPUT
–
PCINT5 INPUT
–
AIO
–
Table 12-5. Overriding Signals for Alternate Functions in PB3..PB0
Signal
Name
PB3/MISO/PCINT3/
PDO
PB2/MOSI/PCINT2/
PDI
PB1/SCK/
PCINT1
PB0/SS/PCINT0
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
SPE • MSTR
PORTB3 • PUD
SPE • MSTR
0
SPE • MSTR
PORTB2 • PUD
SPE • MSTR
0
SPE • MSTR
PORTB1 • PUD
SPE • MSTR
0
SPE • MSTR
PORTB0 • PUD
SPE • MSTR
0
SPE • MSTR
SPI SLAVE OUTPUT
PCINT3 • PCIE0
1
SPE • MSTR
SPI MSTR OUTPUT
PCINT2 • PCIE0
1
SPE • MSTR
SCK OUTPUT
PCINT1 • PCIE0
1
0
0
PCINT0 • PCIE0
1
SPI MSTR INPUT
PCINT3 INPUT
SPI SLAVE INPUT
PCINT2 INPUT
SCK INPUT
SPI SS
DI
PCINT1 INPUT
PCINT0 INPUT
AIO
–
–
–
–
76
7799D–AVR–11/10
ATMEL [ ATMEL ]
