欢迎访问ic37.com |
会员登录 免费注册
发布采购

ATMEGA16U2-MUR 参数 Datasheet PDF下载

ATMEGA16U2-MUR图片预览
型号: ATMEGA16U2-MUR
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有ISP功能的Flash 8/16 / 32K Butes [8-bit Microcontroller with 8/16/32K Butes of ISP Flash]
分类和应用: 微控制器异步传输模式PCATM
文件页数/大小: 310 页 / 4432 K
品牌: ATMEL [ ATMEL CORPORATION ]
 浏览型号ATMEGA16U2-MUR的Datasheet PDF文件第1页浏览型号ATMEGA16U2-MUR的Datasheet PDF文件第2页浏览型号ATMEGA16U2-MUR的Datasheet PDF文件第3页浏览型号ATMEGA16U2-MUR的Datasheet PDF文件第4页浏览型号ATMEGA16U2-MUR的Datasheet PDF文件第6页浏览型号ATMEGA16U2-MUR的Datasheet PDF文件第7页浏览型号ATMEGA16U2-MUR的Datasheet PDF文件第8页浏览型号ATMEGA16U2-MUR的Datasheet PDF文件第9页  
ATmega8U2/16U2/32U2
2.2.5
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of various special features of the ATmega8U2/16U2/32U2 as
listed on
2.2.6
Port D (PD7..PD0)
Port D serves as analog inputs to the analog comparator.
Port D also serves as an 8-bit bi-directional I/O port, if the analog comparator is not used (con-
cerns PD2/PD1 pins). Port pins can provide internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
2.2.7
D-
USB Full Speed Negative Data Upstream Port
2.2.8
D+
USB Full Speed Positive Data Upstream Port
2.2.9
UGND
USB Ground.
2.2.10
UVCC
USB Pads Internal Regulator Input supply voltage.
2.2.11
UCAP
USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac-
itor (1μF).
2.2.12
RESET/PC1/dW
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in
Shorter pulses are not guaranteed to generate a reset. This pin alternatively
serves as debugWire channel or as generic I/O. The configuration depends on the fuses RST-
DISBL and DWEN.
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.2.14
XTAL2/PC0
Output from the inverting Oscillator amplifier if enabled by Fuse. Also serves as a generic I/O.
2.2.13
5
7799E–AVR–09/2012