ATmega8U2/16U2/32U2
1. Pin Configurations
Figure 1-1.
Pinout
32 31 30 29 28 27 26 25
XTAL1
(PC0) XTAL2
GND
VCC
(PCINT11 / AIN2 ) PC2
(OC.0B / INT0) PD0
(AIN0 / INT1) PD1
(RXD1 / AIN1 / INT2) PD2
PC5 ( PCINT9/ OC.1B)
UCAP
PC4 (PCINT10)
AVCC
UVCC
D-
UGND
D+
PB5 (PCINT5)
PB4 (T1 / PCINT4)
PB3 (PDO / MISO / PCINT3)
UCAP
PC4 (PCINT10)
9 10 11 12 13 14 15 16
(RTS / AIN5 / INT6) PD6
(CTS / HWB / AIN6 / T0 / INT7) PD7
(SS / PCINT0) PB0
(INT5/ AIN3) PD4
(XCK / AIN4 / PCINT12) PD5
(SCLK / PCINT1) PB1
(PDI / MOSI / PCINT2) PB2
(TXD1 / INT3) PD3
AVCC
UVCC
D-
UGND
D+
32 31 30 29 28 27 26 25
XTAL1
(PC0) XTAL2
GND
VCC
(PCINT11 /AIN2 ) PC2
(OC.0B / INT0) PD0
(AIN0 / INT1) PD1
(RXD1 / AIN1 / INT2) PD2
PC5 ( PCINT9/ OC.1B)
1
2
3
4
5
6
7
8
QFN32
24
23
22
21
20
19
18
17
Reset (PC1 / dW)
PC6 (OC.1A / PCINT8)
PC7 (INT4 / ICP1 / CLKO)
PB7 (PCINT7 / OC.0A / OC.1C)
PB6 (PCINT6)
1
2
3
4
5
6
7
8
(TXD1 / INT3) PD3
TQFP32
24
23
22
21
20
19
18
17
(SCLK / PCINT1) PB1
(PDI / MOSI / PCINT2) PB2
Reset (PC1 / dW)
PC6 (OC.1A / PCINT8)
PC7 (INT4 / ICP1 / CLKO)
PB7 (PCINT7 / OC.0A / OC.1C)
PB6 (PCINT6)
PB5 (PCINT5)
PB4 (T1 / PCINT4)
PB3 (PDO / MISO / PCINT3)
9 10 11 12 13 14 15 16
(INT5/ AIN3) PD4
(XCK AIN4 / PCINT12) PD5
(RTS / AIN5 / INT6) PD6
/ HWB / AIN6 / T0 / INT7) PD7
(SS / PCINT0) PB0
Note:
The large center pad underneath the QFN package should be soldered to ground on the board to
ensure good mechanical stability.
1.1
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
2
7799E–AVR–09/2012
ATMEL [ ATMEL CORPORATION ]
