ATmega8U2/16U2/32U2
Figure 21-5. USB Device Controller Endpoint Interrupt System
Endpoint 4
Endpoint 3
Endpoint 2
Endpoint 1
Endpoint 0
OVERFI
UESTAX.6
UNDERFI
UESTAX.5
FLERRE
UEIENX.7
NAKINI
UEINTX.6
NAKINE
UEIENX.6
NAKOUTI
UEINTX.4
TXSTPE
Endpoint Interrupt
UEIENX.4
RXSTPI
EPINT
UEINTX.3
UEINT.X
TXOUTE
UEIENX.3
RXOUTI
UEINTX.2
RXOUTE
UEIENX.2
STALLEDI
UEINTX.1
STALLEDE
UEIENX.1
TXINI
UEINTX.0
TXINE
UEIENX.0
Processing interrupts are generated when:
• Ready to accept IN data(EPINTx, TXINI=1)
• Received OUT data(EPINTx, RXOUTI=1)
• Received SETUP(EPINTx, RXSTPI=1)
Exception Interrupts are generated when:
• Stalled packet(EPINTx, STALLEDI=1)
• CRC error on OUT in isochronous mode(EPINTx, STALLEDI=1)
• Overflow(EPINTx, OVERFI=1)
• Underflow in isochronous mode(EPINTx, UNDERFI=1)
• NAK IN sent(EPINTx, NAKINI=1)
• NAK OUT sent(EPINTx, NAKOUTI=1)
21.18 Register Description
21.18.1 UDCON – USB Device Control Registers
Bit
7
-
6
-
5
-
4
-
3
-
2
RSTCPU
R/W
1
RMWKUP
R/W
0
(0xE0)
DETACH
UDCON
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R/W
1
0
0
209
7799D–AVR–11/10
ATMEL [ ATMEL ]
