ATmega8U2/16U2/32U2
It is not possible to have overflow error during IN stage, in the CPU side, since the CPU should
write only if the bank is ready to access data (TXINI=1 or RWAL=1).
21.17 Interrupts
The next figure shows all the interrupts sources:
Figure 21-4. USB Device Controller Interrupt System
UPRSMI
UDINT.6
UPRSME
UDIEN.6
EORSMI
UDINT.5
EORSME
UDIEN.5
WAKEUPI
UDINT.4
WAKEUPE
UDIEN.4
USB Device
Interrupt
EORSTI
UDINT.3
EORSTE
UDIEN.3
SOFI
UDINT.2
SOFE
UDIEN.2
SUSPI
UDINT.0
SUSPE
UDIEN.0
There are 2 kind of interrupts: processing (i.e. their generation are part of the normal processing)
and exception (errors).
Processing interrupts are generated when:
• Upstream resume(UPRSMI)
• End of resume(EORSMI)
• Wake up(WAKEUPI)
• End of reset (Speed Initialization)(EORSTI)
• Start of frame(SOFI, if FNCERR=0)
• Suspend detected after 3 ms of inactivity(SUSPI)
Exception Interrupts are generated when:
• CRC error in frame number of SOF(SOFI, FNCERR=1)
208
7799D–AVR–11/10
ATMEL [ ATMEL ]
