ATmega8U2/16U2/32U2
17. SPI – Serial Peripheral Interface
17.1 Features
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
17.2 Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega8U2/16U2/32U2 and peripheral devices or between several AVR devices.
USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 176.
The Power Reduction SPI bit, PRSPI, in “Minimizing Power Consumption” on page 44 on page
50 must be written to zero to enable SPI module.
Figure 17-1. SPI Block Diagram(1)
DIVIDER
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Note:
1. Refer to Figure 1-1 on page 2, and Table 12-6 on page 77 for SPI pin placement.
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7799D–AVR–11/10
ATMEL [ ATMEL ]
