ATmega8U2/16U2/32U2
Table 15-4 shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to phase
correct PWM mode.
Table 15-7. Compare Output Mode, Phase Correct PWM Mode(1)
COM0B1
COM0B0
Description
0
0
0
1
Normal port operation, OC0B disconnected.
Reserved
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
1
1
0
1
Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
Note:
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 99 for more details.
• Bits 3:2 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 1:0 – WGM0[1:0]: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 15-8. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 96).
Table 15-8. Waveform Generation Mode Bit Description
Timer/Counter
Mode of
Operation
Update of
OCRx at
TOV Flag
Mode
WGM2
WGM1
WGM0
TOP
Set on(1)(2)
0
0
0
0
Normal
0xFF
Immediate
TOP
MAX
PWM, Phase
Correct
1
0
0
1
0xFF
BOTTOM
2
3
4
0
0
1
1
1
0
0
1
0
CTC
OCRA
0xFF
–
Immediate
MAX
MAX
–
Fast PWM
Reserved
TOP
–
PWM, Phase
Correct
5
1
0
1
OCRA
TOP
BOTTOM
6
7
1
1
1
1
0
1
Reserved
Fast PWM
–
–
–
OCRA
TOP
TOP
Notes: 1. MAX = 0xFF
2. BOTTOM = 0x00
104
7799D–AVR–11/10
ATMEL [ ATMEL ]
