ATmega169P
18.1 Overview
A simplified block diagram of the USART Transmitter is shown in Figure 18-1. CPU accessible
I/O Registers and I/O pins are shown in bold.
Figure 18-1. USART Block Diagram(1)
Clock Generator
UBRR[H:L]
OSC
BAUD RATE GENERATOR
SYNC LOGIC
PIN
XCK
CONTROL
Transmitter
TX
CONTROL
UDR (Transmit)
PARITY
GENERATOR
PIN
CONTROL
TRANSMIT SHIFT REGISTER
TxD
Receiver
CLOCK
RX
RECOVERY
CONTROL
DATA
RECOVERY
PIN
CONTROL
RECEIVE SHIFT REGISTER
RxD
PARITY
CHECKER
UDR (Receive)
UCSRA
UCSRB
UCSRC
Note:
1. Refer to Figure 1-1 on page 2, Table 12-13 on page 80, and Table 12-7 on page 76 for USART
pin placement.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.
The Clock Generation logic consists of synchronization logic for external clock input used by
synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only
used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial
Shift Register, Parity Generator and Control logic for handling different serial frame formats. The
write buffer allows a continuous transfer of data without any delay between frames. The
Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level
receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
169
8018A–AVR–03/06
ATMEL [ ATMEL ]
