TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state
machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4.
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is
enabled, this pin can not be used as an I/O pin.
• ADC3 – ADC0 – Port F, Bit 3..0
Analog to Digital Converter, Channel 3..0.
Table 43. Overriding Signals for Alternate Functions in PF7..PF4
Signal
Name
PUOE
PUOV
DDOE
DDOV
PF7/ADC7/TDI
PF6/ADC6/TDO
JTAGEN
0
PF5/ADC5/TMS
PF4/ADC4/TCK
JTAGEN
JTAGEN
JTAGEN
1
1
1
JTAGEN
0
JTAGEN
JTAGEN
0
JTAGEN
0
SHIFT_IR +
SHIFT_DR
PVOE
PVOV
DIEOE
DIEOV
DI
0
JTAGEN
0
0
0
TDO
0
0
JTAGEN
JTAGEN
JTAGEN
JTAGEN
0
–
0
–
0
–
0
–
AIO
TDI/ADC7 INPUT ADC6 INPUT
TMS/ADC5
INPUT
TCKADC4 INPUT
Table 44. Overriding Signals for Alternate Functions in PF3..PF0
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
PF3/ADC3
PF2/ADC2
PF1/ADC1
PF0/ADC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
–
–
–
AIO
ADC3 INPUT
ADC2 INPUT
ADC1 INPUT
ADC0 INPUT
84
ATmega128(L)
2467P–AVR–08/07
ATMEL [ ATMEL ]
