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ATMEGA128L-8AL 参数 Datasheet PDF下载

ATMEGA128L-8AL图片预览
型号: ATMEGA128L-8AL
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, 8MHz, CMOS, PQFP64, 14 X 14 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026AEB, TQFP-64]
分类和应用: 时钟微控制器外围集成电路
文件页数/大小: 391 页 / 6192 K
品牌: ATMEL [ ATMEL ]
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ATmega128(L)  
Alternate Functions of In ATmega103 compatibility mode, only the alternate functions are the defaults for Port G, and  
Port G  
Port G cannot be used as General Digital Port Pins. The alternate pin configuration is as follows:  
Table 45. Port G Pins Alternate Functions  
Port Pin  
PG4  
Alternate Function  
TOSC1 (RTC Oscillator Timer/Counter0)  
TOSC2 (RTC Oscillator Timer/Counter0)  
ALE (Address Latch Enable to external memory)  
RD (Read strobe to external memory)  
WR (Write strobe to external memory)  
PG3  
PG2  
PG1  
PG0  
• TOSC1 – Port G, Bit 4  
TOSC1, Timer Oscillator pin 1: When the AS0 bit in ASSR is set (one) to enable asynchronous  
clocking of Timer/Counter0, pin PG4 is disconnected from the port, and becomes the input of the  
inverting Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and the  
pin can not be used as an I/O pin.  
• TOSC2 – Port G, Bit 3  
TOSC2, Timer Oscillator pin 2: When the AS0 bit in ASSR is set (one) to enable asynchronous  
clocking of Timer/Counter0, pin PG3 is disconnected from the port, and becomes the inverting  
output of the Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and  
the pin can not be used as an I/O pin.  
• ALE – Port G, Bit 2  
ALE is the external data memory Address Latch Enable signal.  
• RD – Port G, Bit 1  
RD is the external data memory read control strobe.  
• WR – Port G, Bit 0  
WR is the external data memory write control strobe.  
Table 46 and Table 47 relates the alternate functions of Port G to the overriding signals shown in  
Figure 33 on page 71.  
Table 46. Overriding Signals for Alternate Functions in PG4..PG1  
Signal Name  
PUOE  
PUOV  
DDOE  
DDOV  
PVOE  
PVOV  
DIEOE  
DIEOV  
DI  
PG4/TOSC1  
PG3/TOSC2  
PG2/ALE  
PG1/RD  
AS0  
AS0  
SRE  
0
SRE  
0
0
0
AS0  
AS0  
SRE  
1
SRE  
1
0
0
0
0
SRE  
ALE  
0
SRE  
RD  
0
0
0
AS0  
AS0  
0
0
0
0
AIO  
T/C0 OSC INPUT  
T/C0 OSC OUTPUT  
85  
2467P–AVR–08/07  
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