Table 37. Overriding Signals for Alternate Functions PD7..PD4
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
PD7/T2
PD6/T1
PD5/XCK1
PD4/ICP1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
UMSEL1
0
0
0
XCK1 OUTPUT
0
0
0
0
0
0
0
0
0
T2 INPUT
–
T1 INPUT
–
XCK1 INPUT
–
ICP1 INPUT
–
AIO
Table 38. Overriding Signals for Alternate Functions in PD3..PD0(1)
Signal Name PD3/INT3/TXD1 PD2/INT2/RXD1
PD1/INT1/SDA
PD0/INT0/SCL
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
TXEN1
RXEN1
TWEN
TWEN
0
PORTD2 • PUD
PORTD1 • PUD PORTD0 • PUD
TXEN1
RXEN1
TWEN
TWEN
1
0
SDA_OUT
SCL_OUT
TWEN
TXEN1
0
TWEN
TXD1
0
0
0
INT3 ENABLE
INT2 ENABLE
1
INT1 ENABLE
1
INT0 ENABLE
1
1
INT3 INPUT
–
INT2 INPUT/RXD1 INT1 INPUT
– SDA INPUT
INT0 INPUT
SCL INPUT
AIO
Note:
1. When enabled, the Two-wire Serial Interface enables Slew-Rate controls on the output pins
PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between
the AIO outputs shown in the port figure and the digital logic of the TWI module.
80
ATmega128(L)
2467P–AVR–08/07
ATMEL [ ATMEL ]
