The following code example shows one assembly and one C function for turning off the WDT.
The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that
no interrupts will occur during execution of these functions.
Assembly Code Example
WDT_off:
; Reset WDT
wdr
in r16, WDTCR
; Write logical one to WDCE and WDE
ori r16, (1<<WDCE)|(1<<WDE)
out WDTCR, r16
; Turn off WDT
ldi r16, (0<<WDE)
out WDTCR, r16
ret
C Code Example
void WDT_off(void)
{
/* Reset WDT*/
__watchdog_reset();
/* Write logical one to WDCE and WDE */
WDTCR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCR = 0x00;
}
Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing configuration differs slightly between the three safety levels. Sepa-
rate procedures are described for each level.
Safety Level 0
Safety Level 1
This mode is compatible with the Watchdog operation found in ATmega103. The Watchdog
Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction.
The time-out period can be changed at any time without restriction. To disable an enabled
Watchdog Timer, the procedure described on page 56 (WDE bit description) must be followed.
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit
to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out
period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, and/or
changing the Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written
to WDE regardless of the previous value of the WDE bit.
2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as
desired, but with the WDCE bit cleared.
Safety Level 2
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A
timed sequence is needed when changing the Watchdog Time-out period. To change the
Watchdog Time-out, the following procedure must be followed:
58
ATmega128(L)
2467P–AVR–08/07
ATMEL [ ATMEL ]
