ATmega128(L)
Voltage Reference
Enable Signals and
Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in Table 20. To save power, the reference is not always turned on. The ref-
erence is on during the following situations:
1. When the BOD is enabled (by programming the BODEN fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
ACBG bit in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
Table 20. Internal Voltage Reference Characteristics
Symbol
VBG
Parameter
Min
Typ
1.23
40
Max
1.40
70
Units
V
Bandgap reference voltage
Bandgap reference start-up time
Bandgap reference current consumption
1.15
tBG
µs
IBG
10
µA
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 Mhz. This is
the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in Table 22 on page 57. The WDR – Watchdog Reset – instruction resets the Watchdog
Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega128 resets and executes from the
Reset Vector. For timing details on the Watchdog Reset, refer to page 54.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, 3
different safety levels are selected by the Fuses M103C and WDTON as shown in Table 21.
Safety level 0 corresponds to the setting in ATmega103. There is no restriction on enabling the
WDT in any of the safety levels. Refer to “Timed Sequences for Changing the Configuration of
the Watchdog Timer” on page 58 for details.
55
2467P–AVR–08/07
ATMEL [ ATMEL ]
